The role of PCB stack in controlling EMI radiation
This paper discusses the role and design technology of PCB stack in controlling EMI emission from a basIC<a href="/tw/pcb board. html" target="_blank">PCB layout
Power busbar
The output voltage of the IC can change quickly if a capacitor of appropriate capacity is placed reasonably near the power supply pin of the IC. However, this is not the end of the problem. Due to the limited frequency response of capacitors, this blocks them from generating the required harmonic power, thus driving the IC output cleanly across the entire frequency band. In addition, the transient voltage generated on the power bus will cause voltage drop on the inductance of the decoupling path. These transient voltages are the main source of common mode EMI interference. How should we solve these problems? When there is an IC on our circuit board, the power plane around the IC can be considered as a good high-frequency capacitor, which can collect the energy leaked by discrete capacitors and provide high-frequency energy for clean output. In addition, the inductance of the good power supply layer should be SMAll, and the transient signal synthesized by this inductor is also small, thus reducing the common mode EMI. Of course, the connection from the power layer to the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster, it is directly connected to the bonding pad where the IC power supply pin is located, which will be discussed separately.

In order to control common mode EMI, the power plane must be a pair of power planes with reasonable design, so as to decouple, and have a sufficiently low inductance. Some may ask, how good is it? The answer to this question depends on the power supply layer, inter layer data and operating frequency (i.e., a function of IC rise time). Generally, the spacing between power layers is 6mil, the intermediate layer is FR4 data, and the equivalent capacitance of power layers per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance. There are not many devices with a rise time between 100 and 300 ps, but according to the current development speed of integrated circuits, devices with a rise time between 100 and 300 ps will account for a large proportion. For circuits with rise times of 100 to 300 ps, 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use layered technology with layer spacing less than 1 mil and replace FR4 dielectric material with very high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300 ps rise time circuits. Although new data and methods may be adopted in the future, the common 1 to 3 ns rise time circuit, 3 to 6 mil layer spacing and FR4 dielectric data today are usually enough to handle high-end harmonics and keep the transient at a sufficiently low level, that is, the common mode EMI may be very low. The PCB layered stacking design example given in this paper will assume a layer spacing of 3 to 6 mils.
Electromagnetic mask
From the point of view of signal routing, a good layering strategy should be to place all signal traces on one or more layers near the power source or ground plane. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer should be as small as possible. This is what we call "layering" strategy.
PCB stacking
Which stacking strategies help mask and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer and that a single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power planes will be discussed later.
4-layer plate
There are several potential problems in the design of 4-ply panels. First of all, for the traditional four layer plate with a thickness of 62 mils, even if the signal layer is in the outer layer and the power layer and the ground layer are in the inner layer, the distance between the power layer and the ground layer is still too large. If there is a cost requirement, consider the following two methods to replace the traditional 4-layer plate. Both solutions can improve the EMI suppression efficiency, but only when the component density on the circuit board is low enough and there is enough area around the component (where the copper layer of the required power supply is placed), can the EMI suppression efficiency be improved. The outer layer of PCB is the ground plane, and the middle two layers are the signal/power layer. The power supply on the signal layer uses wide trace wiring, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path low. From the perspective of EMI control, this is the existing 4-layer PCB structure. In the second scheme, the outer layer receives power and ground, and the middle two layers receive signals. Compared with the traditional 4-layer plate, the improvement range of this scheme is small, and the interlayer impedance is as bad as that of the traditional 4-layer plate. If trace impedance is to be controlLED, the above stacking scheme requires very careful routing of traces under power and ground copper islands. In addition, copper islands on the power supply or ground plane should be interconnected as closely as possible to ensure DC and low-frequency connections.
6-layer plate
If the element density on the 4-layer board is relatively high, the 6-layer board is used. However, some stacking schemes in the 6-layer Board Design are not enough to mask the electromagnetic field and have little effect on reducing the transient signal of the power bus. Two examples are discussed below. In the first example, the power and ground are located on the second and fifth layers, respectively. Due to the high impedance of the copper coating of the power supply, it is difficult to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct. The second example places power and ground on the third and fourth layers respectively. This design solves the problem of copper cladding impedance of power supply. Due to the poor performance of the electromagnetic masks in Layer 1 and Layer 6, differential mode EMI will be added. If the number of signal lines on the two outer layers is small and the trace length is short (less than 1/20 of the signal harmonic wavelength), the design can solve the differential mode EMI problem. The suppression effect of differential mode EMI is particularly good by filling the non component and non trace areas on the outer layer with copper and grounding the copper clad area (every 1/20 wavelength is an interval). As previously mentioned, the copper area should be connected to the internal ground plane at multiple points. In general, the first and sixth layers of high-performance 6-layer board are generally arranged as ground layers, and the third and fourth layers are power layers and ground layers. Since there are two central double microstrip signal line layers between the power supply and the ground plane, this EMI suppression effect is very good. The disadvantage of this design is that there are only two layers of traces. As mentioned earlier, if the outer layer trace is short and the copper is placed in the traceless area, the traditional 6-layer plate can also achieve the same stacking. Another 6-layer circuit board layout is signal, grounding, signal, power, grounding, signal, which provides the required environment for signal integrity design. The signal layer is adjacent to the ground plane, and the power supply is paired with the ground plane. Obviously, the disadvantage is that the layers are stacked unevenly. This usually brings trouble to the manufacturing industry. The solution to this problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or ground plane after copper filling, the board can be loosely counted as a circuit board with balanced structure. The copper filled area must be connected to power or ground. The distance between connecting vias is still 1/20 wavelength, which may not be everywhere, but it should be connected ideally.
10 ply board
Due to the very thin insulation layer between the multilayer boards, the interlayer impedance of the 10 or 12 layer boards is very low, and as long as there is no layering and stacking problems, good signal integrity can be expected. It is more difficult to make 12 ply plates with a thickness of 62 mils, and there are few manufacturers that can process 12 ply plates. Since there is always an insulating layer between the signal layer and the loop layer, this is not the solution that allocates the middle 6 layers to wire the signal lines in the 10 layer board design. In addition, the signal layer must be adjacent to the loop layer, that is, the circuit board layout is signal, grounding, signal, signal, power supply, grounding, signal, signal, grounding, signal. This design provides a good path for signal current and its loop current. The correct routing strategy is to route the first layer along the X direction, the third layer along the Y direction, the fourth layer along the X direction, and so on. Visually, the first and third layers are a pair of layered combinations, the fourth and seventh layers are a pair of layered combinations, and the eighth and tenth layers are the latter pair of layered combinations. When it is necessary to change the direction of the trace, the signal line on the first layer should be "through-hole" to the third layer, and then change the direction. In practice, this may not always be possible, but as a design, the concept tries to adhere to it. SIMilarly, when the wiring direction of the signal changes, it should pass through the vias of the 8th and 10th layers or the 4th to 7th layers. This routing ensures a tight coupling between the forward path and the return path of the signal. For example, if the signal is routed to Layer 1, and the loop is routed to Layer 2 and only to Layer 2, then even if the signal on Layer 1 reaches Layer 3 through the "through-hole", the loop is still on Layer 2, thus maintaining low inductance, high capacitance and good electromagnetic shielding efficiency. What if the actual wiring is not like this? For example, the signal line on the first layer passes through the through-hole to reach the tenth layer. At this time, the loop signal must find the ground plane from the ninth layer, and the loop current needs to find the nearest ground through the hole (such as the grounding pin of resistor or capacitor and other components). If you happen to have such a passage nearby, you are really lucky. If there is no such tight through-hole, the inductance will increase, the capacitance will decrease, and EMI will certainly increase. When the signal line must leave the current pair of wiring layers to other wiring layers through the vias, the grounding vias should be placed near the vias so that the loop signal can return to the corresponding grounding layer smoothly. For the combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitive coupling between the power layer and ground layer is good, and the signal is easy to transmit.
Multi power layer design
If two power supply planes of the same voltage source need to output large current, the circuit board shall be arranged in two groups of power supply planes and ground plane. In this case, place an insulating layer between each pair of power supplies and the ground plane. Through this pipe, we get two pairs of power buses with equal impedance, and we expect to distribute the current evenly. If the stack of power planes produces unequal impedances, the shunt will be uneven, the transient voltage will be greater, and EMI will increase significantly. If there are multiple power supply voltages with different values on the circuit board, multiple power planes are required. Remember to create your own paired power supply and ground plane for different power supplies. In the above two cases, when determining the position of the matching power supply and ground plate on the circuit board, please remember the manufacturer's requirements for the balanced structure.
Summary
Considering that most engineers design the circuit board as a traditional printed circuit board with a thickness of 62 mils, and there is no blind hole or embedded via, the discussion on the layering and stacking of circuit boards is limited to this For plates with large thickness difference, the delamination scheme recommended in this paper may not be ideal In addition, the layering method in this paper is not applicable to PCB with blind holes or embedded holes due to different processing pipes Thickness, via process and the number of circuit board layers in circuit board design are not the key to solve the problem Excellent layered stacking can ensure that the bus bar so that this transient voltage on the power plane or the ground plane is not affected The key to shielding the electromagnetic fields of signals and power there should be an insulating isolation layer between the signal trace layer and its return ground layer, and the paid layer spacing (or more than one pair) should be as small as possible Based on these basic concepts and principles, the PCB can always meet the design requirements Now, the rise time of IC is shorter, and it will also be shorter in the future. The technology discussed in this paper is crucial to solving the EMI mask problem