Check point introduction of PCB design, to guide you to prepare for takeoff

1、 Data input stage

1. Whether the data received on the process are complete (including schematIC diagram, *. brd file, bill of materials, PCB design description, PCB design or change requirements, standardization requirements description, process design description document)

2. Confirm that the PCB template is up to date

3. Confirm that the position of the positioner of the template is correct

4. Whether PCB design description, PCB design or change requirements, and standardization requirements are clear

5. Confirm that the prohibited components and wiring areas on the outline drawing have been reflected on the PCB template

6. Compare the outline drawing to confirm that the dimensions and tolerances MARKed on the PCB are correct, and the definition of metallized holes and nonmetallic holes is accurate

7. After confirming that the PCB template is correct, it is better to lock the structure file to avoid misoperation of the moved position

2、 Post layout inspection phase

a. Component inspection

8. Confirm whether the package of all devices is consistent with the company's unified library, and whether the package library has been updated (check the operation results with the viewlog). If not, be sure to update the symbols and other system settings.

9. Motherboard and daughter board, single board and backplane, confirm that the signals and positions are corresponding, the connector direction and silk screen identification are correct, the daughter board has anti misplug measures, and the components on the daughter board and motherboard should not interfere

10. Whether components are placed 100%

11. Open the place ground of TOP and BOTTOM layers of the device, and check whether DRC caused by overlap is allowed

12. Is Mark point sufficient and necessary

13. Heavy components should be placed close to PCB support points or edges to reduce PCB warpage

14. It is better to lock the components related to the structure after the layout to prevent misoperation of the moving position

15. Within the range of 5mm around the crimping socket, no components with a height higher than the crimping socket are allowed on the front, and no components or welding spots are allowed on the back

16. Confirm whether the device layout meets the technological requirements (focus on BGA, PLCC and SMD socket)

17. Special attention shall be paid to components with metal shell not to collide with other components, and enough space shall be reserved

18. The components related to the interface shall be placed as close to the interface as possible, and the backplane bus driver shall be placed as close to the backplane connector as possible

19. Whether the chip device on the wave soldering surface has been converted to wave soldering package,

20. Whether there are more than 50 manual welding points

21. Horizontal installation should be considered for axial insertion of higher components on PCB. Leave room for lying. And consider the fixing mode, such as the fixed pad of crystal oscillator

22. For components requiring heat sink, confirm that there is enough space between them and other components, and pay attention to the height of main components within the range of heat sink

b. Functional check

23. Whether the digital circuit and analog circuit components of the digital analog mixing board have been separated in layout, and whether the signal flow is reasonable

24. The A/D converter is placed across the A/D partition.

25. Whether the layout of clock devices is reasonable

26. Whether the layout of high-speed signal devices is reasonable

27. Whether the termination devices have been properly placed (the source matching serial resistance should be placed at the driving end of the signal; the middle matching serial resistance should be placed at the middle position; the terminal matching serial resistance should be placed at the receiving end of the signal)

28. Whether the number and position of decoupling capacitors of IC devices are reasonable

29. The signal line takes the plane of different levels as the reference plane. When crossing the plane division area, whether the connection capacitance between the reference planes is close to the signal routing area.

30. Whether the layout of the protection circuit is reasonable and conducive to division

31. Is the fuse of the board power supply placed near the connector without any circuit elements in front

32. Confirm that strong signal and weak signal (power difference of 30dB) circuits are laid separately

33. Whether the components that may affect the EMC experiment are placed according to the design guide or reference to successful experience. For example, the reset circuit of the panel should be slightly close to the reset button

c. Fever

34. Heat sensitive components (including liquid medium capacitors and crystal oscillators) shall be kept away from high-power components, radiators and other heat sources as far as possible

35. Whether the layout meets the thermal design requirements, and the heat dissipation channel (according to the process design documents)

d. Power supply

36. Is the IC power supply too far from the IC

37. Whether the layout of LDO and surrounding circuits is reasonable

38. Whether the circuit layout around the module power supply is reasonable

39. Whether the overall layout of the power supply is reasonable

e. Rule Settings

40. Whether all SIMulation constraints have been correctly added to the Constraint Manager

41. Whether the physical and electrical rules are set correctly (pay attention to the constraint settings of power network and ground network)

42. Is the spacing between Test Via and Test Pin sufficient

43. Whether the thickness and scheme of the lamination meet the design and processing requirements

44. Whether all differential line impedances with characteristic impedance requirements have been calculated and controlLED by rules

3、 Post wiring inspection phase

e. Digital analog

45. Whether the routing of digital circuit and analog circuit has been separated, and whether the signal flow is reasonable

46. If the A/D, D/A and similar circuits are separated from the ground, does the signal line between the circuits go from the bridge point between the two grounds (except the differential line)?

47. Signal lines that must cross the gap between divided power supplies shall refer to the complete ground plane.

48. If the stratigraphIC design zoning is adopted, ensure that the digital signal and analog signal are wired in zones.

f. Clock and high-speed part

49. Whether the impedance of each layer of high-speed signal line is consistent

50. Are high-speed differential signal lines and similar signal lines of equal length, symmetrical and parallel?

51. Make sure that the clock line is in the inner layer as far as possible

52. Confirm whether clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired according to the principle of 3W as far as possible

53. Is there no bifurcated test point on the clock, interrupt, reset signal, 100M/Gigabit Ethernet, and high-speed signal?

54. Is 10H between low level signals such as LVDS and TTL/CMOS signals as much as possible (H is the height of the signal line from the reference plane)?

55. Do clock cables and high-speed signal cables avoid routing through areas with dense through-hole or device pins?

56. Whether the clock line has met the requirements (SI constraints) (whether the clock signal routing has achieved less vias, short routing, and continuous reference planes, and the main reference plane is GND as far as possible; if the GND main reference plane layer is changed during layer change, it is GND vias within the range of 200mil from the vias). If the main reference planes of different levels are changed during layer change, whether there is decoupling capacitance within the range of 200mil from the vias)?

57. Whether differential pairs, high-speed signal lines and various BUS have met the requirements (SI constraints)

PCB manufacturers, PCB designers and PCBA manufacturers will explain the checkpoints of PCB design to you, and guide you to prepare for takeoff.